ENEE459D: Topics in Computer Engineering; Advanced Laboratory of Digital SystemVerilog

Credits: 3

Description

Prerequisite: Completion of ENEE245 and ENEE350 with a C- or better.

This project-oriented course will cover the basics of verifying hardware description language (HDL) digital systems, from theory to industry practice, and the implementation by a FPGA board. Laboratory exercises will deal with applications of the concepts taught, and these will be based on verification tools currently used in industry and SystemVerilog, a hardware description and hardware verification language. The lectures will discuss the basics of verification, starting with combinational logic, and include function representations based on digital design diagrams, finite state machines, as well as processors.

Semesters Offered

Fall 2019, Fall 2020, Spring 2021, Summer 2021, Fall 2021, Spring 2022, Fall 2022, Spring 2023, Fall 2023, Spring 2024
Testudo

Additional Course Information

Description

Prerequisite: Completion of ENEE245 and ENEE350 with a "C-" or better.
Restriction: Open to Electrical and Computer Engineering majors only.

A project-oriented course that will cover the basics of verifying hardware description language (HDL) digital systems, from theory to industry practice. Laboratory exercises will deal with applications of the concepts taught, and these will be based on verification tools currently used in industry and SystemVerilog, a hardware description and hardware verification language. A GUI interface verification environment will be designed by using object-oriented programming lanuage (C/C++).

Course Goals

This project-oriented course will cover the basics of verifying hardware description language (HDL) digital systems, from theory to industry practice. Laboratory exercises will deal with applications of the concepts taught, and these will be based on verification tools currently used in industry and SystemVerilog, a hardware description and hardware verification language. A GUI interface verification environment will be design by using object-oriented programming language (C/C++). 
 
The lectures will discuss the basics of verification, starting with combinational logic, and include function representations based on digital design diagrams, as well as the finite state machines. This will be followed by a comprehensive overview of SystemVerilog. 
 
The fundamental concepts will be supplemented by examples of industry practice. These will include verification flows in industry, verification testbenches, and Universal Verification Methodology (UVM). 
 
Assignments and laboratory exercises using commercial tools will be assigned to reinforce the concepts discussed in class. There will be one in class midterm exam. A group project, dealing with some aspect of verification, will be required and presented in
the class.

 

Course Topics

  • Digital design flow with ASICs and FPGAs
  • Introduction to hardware verification
  • SystemVerilog coding
  • Verification of combinational logic designs
  • Verification of sequencial logic designs
  • Verification of Finite State Machines
  • PLI and integrated object-oriented programming language (C/C++)
  • GUI interface of the verification environments
  • Generation of test signals for the FPGA environment

Course Objectives

  • Experience with advanced verification of digital system design
  • Advanced SystemVerilog HDL-based design
  • Use of associated CAD tools
  • FPGA implementation and testing
  • Project work and experimentation
    • Design, coding, simulation, and synthesis
    • Implementation and debugging on FPGAs
    • Experiment design
    • Project report and oral presentation
  • Teamwork experience
  • Communication skill development
    • Oral presentations
    • Written reports