Credits: 3
State-of-the-art techniques and algorithms for synthesis and verification of digital systems. High-level and architectural synthesis,decision and word-level algorithms, combinational and sequential logic optimization. Formal and simulation-based verification techniques; combinational and sequential equivalence checking; model and property checking; satisfiability (SAT) and satisfiability modulo theories (SMT).
Description
Prerequisite: ENEE245 and ENEE350; or students who have taken courses with comparable content may contact the Department.State-of-the-art techniques and algorithms for synthesis and verification of digital systems. High-level and architectural synthesis,decision and word-level algorithms, combinational and sequential logic optimization. Formal and simulation-based verification techniques; combinational and sequential equivalence checking; model and property checking; satisfiability (SAT) and satisfiability modulo theories (SMT).
Semesters Offered
Fall 2024
Testudo